The present invention relates to digital circuits. In particular, the present invention relates to clocking schemes for digital circuits.
Low power has emerged as a major issue in the electronics industry. Previously, the major concerns in microelectronics were performance, area, cost, and reliability, with power generally only of importance if some cooling limit were being exceeded or if devices were battery operated. As chip densities and clock speeds increase, and as more and more equipment are made portable and battery operated, power consumption has become of critical importance.
A primary component of power dissipation in CMOS logic circuitry is active power dissipation. Active power dissipation (disregarding contributions from DC and non-capacitive currents, such as short-circuit currents) is calculated by P=C*V.sub.dd.sup.2 *f, where P is power, C is load capacitance, V.sub.dd is the power-supply voltage, and f is the switching frequency at which the circuit is operated.
Active power dissipation is most directly influenced by the magnitude of the supply voltage V.sub.dd. Thus, a trend among digital designers is to reduce the supply voltage. However, the amount by which the supply voltage can be reduced is limited so that further gains along this avenue are difficult to achieve.
Although reductions in the switching frequency may also result in reduced active power dissipation, such a reduction is at odds with the need for increased device operating speeds. This problem is compounded by the increased use of synchronous devices, such as synchronous dynamic or static memory devices (SDRAMs or SSRAMs). These synchronous devices employ a master clock which controls all features of a device. For example, in a synchronous SRAM, the master clock controls the input, storage, and output of data from the memory. Active power dissipation is increased due to the need to route the high frequency master clock signal throughout the device. This power dissipation, however, is generally accepted as a necessary expense to attain high frequencies of operation.
It is desirable to reduce the active power dissipation in such a device while permitting high frequency operation.